1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a technology for forming a pattern on a W/WN/polysilicon layered film structure by using a dry etching technique.
2. Description of the Related Art
Gate electrodes are designed to have a lower wiring resistance and a smaller thickness to match the request for a higher integration density and a higher performance of semiconductor integrated circuits. As a gate electrode structure for realizing the lower wiring resistance and the smaller film thickness, there is known a polysilicon-metal structure in which a high-melting-point metal layer is stacked on a Poly-Si (polysilicon:polycrystalline silicon) layer. A polysilicon-metal gate electrode structure having a W/WN/Poly-Si/SiO2 layered film has been developed, in which the SiO2 film is used for a gate insulating film underlying the gate electrode structure, the W layer is used as a high-melting-point metal film, and the WN layer is interposed as a barrier metal film between the W layer and the Poly-Si layer.
The gate electrode structure having the W/WN/Poly-Si/SiO2 layered film, as shown in FIG. 3, is manufactured by forming a mask 23 made of an insulating film on the W/WN/Poly-Si/SiO2 layered film 10 and patterning the layered film 10 by using a dry etching technique. Such a method for manufacturing the gate electrode is described in, for example, Jpn. Pat. Appln. Publication Nos. 2000-40696 and 2003-78034.
In the above patent documents, the dry etching technique is used as a first step wherein metal layers, such as the W layer 15 and WN layer 14, are etched by using plasma generated in mixed gas containing SF6. Thereafter, in a second step, the Poly-Si layer 13 is etched by using plasma generated in mixed gas containing Cl2 and Ar. Subsequently, in a third step, residues of the Poly-Si layer 13 are etched while maintaining a high selectivity ratio of the Poly-Si layer 13 from the SiO2 layer 12 by using plasma generated in mixed gas containing HBr and O2.
In a DRAM (Dynamic Random Access Memory) having a gate width of 110 nm for a next generation, the thickness of the layered film is extremely reduced in order to raise the operational speed of the semiconductor device, wherein the design thickness of the Poly-Si layer 13 is 70 nm or less, and the design thickness of the gate oxide film made of SiO2 is 4 nm or less, for example. For using the manufacturing methods described in the above patent documents in the semiconductor device having such a gate electrode structure, there occurs a problem of so-called “penetration of SiO2 layer” wherein the SiO2 layer is broken by penetration during the etching process in the second or third step. Although the problem of penetration of the SiO2 layer is also described in the above patent documents, it is difficult to effectively suppress the penetration of the SiO2 layer in the process of manufacturing the gate electrode structure having the above-described thin SiO2 layer 12 and Poly-Si layer 13.